1. Field of the Invention
The disclosed technology relates to improvements in or relating to time stamp generation, and is more particularly concerned with time stamp generation in time-to-digital converters.
2. Description of the Related Technology
Time stamps are normally generated in two portions, namely, a coarse part corresponding to the most significant bits (MSBs) and a fine part corresponding to the least significant bits (LSBs). In general, the coarse and fine parts of a time stamp are generated using two different techniques. The MSBs are obtained by counting the number of elapsed clock cycles between a reference instant and the event to be measured, and the LSBs are generated by dividing the clock period in smaller time intervals and identifying in which smaller time interval the event has happened. In an actual implementation, the MSBs can be generated by adopting a NMBS-bit binary counter circuit running at the frequency fclk. The LSB part is typically generated by using a delay locked loop (DLL) circuit operating at frequency fclk. The DLL generates 2NLSB equally spaced clock phases. At the instant in which the event to be measured occurs, the DLL phases are sampled and stored in a 2NLSB-bit register. The word in the register is then decoded using thermometer-to-binary decoding to provide an nLSB-bit word corresponding to the binary representation of the fine time stamp. The fine time stamp identifies the DLL phase, to within one clock period, in which the event occurred. In the case of a multi-channel system, only single DLL is required. The sampling and decoding of the DLL phases instead has to be performed in each channel independently.
Ideally, there should be no phase difference between the coarse counter clock and the clock used by the DLL, but in practice, there is always a skew between the clock of the coarse counter and that of the DLL. This is inherent in any implementation on silicon. This is because signal propagation delays can become comparable with the DLL resolution.
U.S. Pat. No. 5,166,959 describes a time-to-digital converter (TDC) implementation in which two coarse counters clocked with two clocks in opposition of phase (lead and lag clocks) and a DLL. The two counters lead and lag the clock used by the DLL. The DLL clock is skewed by ¼ of the clock period with respect to the lead/lag clocks. When an event occurs, both lead and lag counters are sampled, but only one of them is stored. The first phase produced by the DLL determines which coarse time stamp is to be stored. The alignment between coarse and fine time stamps is guaranteed by choosing the correct time stamps among those produced by the two coarse counters. The alignment between the coarse part and fine part of the time stamp is guaranteed only when the skew between the coarse part and fine part of the DLL clocks does not exceed ±4 LSBs. When this implementation is used in a multi-channel system, it does not provide consistent time stamps for events occurring simultaneously in more than one channel. If the coarse and fine clocks present different skews in different channels, different time stamps are generated for events occurring at the same instant in different channels. The skew between the coarse and fine clock has to stay within ±¼ of the coarse clock period.
In WO-A-2007/093221, the TDC implementation is based on a ring oscillator, for example, a closed loop delay line, or on a combination of Vernier delay lines, for example, an open loop delay line. A calibration technique is used to guarantee linearity at the boundaries between fine and coarse time stamps in which two reference clock edges are injected into the Vernier delay line after every measured pulse. By sampling the status of the Vernier delay line at the two calibration edges, the actual position of the coarse clock edges with respect to the ideal position is measured and used to correct the final fine time stamp. The final time stamp is obtained by multiplying the measured fine time stamp by the correction.
In U.S. Pat. No. 5,838,754, the TDC implementation adopts a Vernier delay line to generate fine time stamps. When combined with a coarse counter, the misalignment between coarse and fine time stamps is prevented by having the coarse counter count both edges of the clock signal in order to provide a redundant bit between the coarse and fine time stamps. If the redundant bit is not equal, than the coarse time stamp is corrected before combining it with the fine time stamp. The alignment is guaranteed only if the skew between the coarse and fine clocks does not exceed ±¼ of the coarse clock period. When used in a multi-channel system, events occurring simultaneously in more than one channel do not have the same time stamp. Indeed, if the coarse and fine clocks present different skews in different channels, different time stamps are generated for events occurring at the same instant in different channels.
If offset correction is not been carried out using the correct offset value, the impact on the final time stamp produces an error known as rollover.